The invention relates to a circuit arrangement for the correction of step distortions in a data transmission employing frequency-modulated data signals. A demodulator is provided which compares the time durations between edges of the frequency-modulated data signals with a measuring time duration generated by means of a timing element and generates demodulated data signals after filtering, these demodulated data signals exhibiting step distortions as a result of frequency deviations of the frequency-modulated data signals.
A demodulator for a demodulation of frequency-modulated data signals is known from the German AS No. 2,606,515, incorporated herein by reference, said demodulator generating signals which are proportional to the difference between the time duration between two respective edges or zero passages of the frequency-modulated data signals and a constant measuring time duration. These signals are integrated upon employment of a low pass filter, and converted into binary demodulated data signals by means of a threshold value stage. The binary values of these demodulated data signals are allocated to the characteristic frequencies of the frequency-modulated data signals.
For generating the measuring time duration, the known circuit arrangement contains a timing element which is designed as a counter which is counted forward by means of clock pulses with a constant repetition frequency. At edges or zero passages of the frequency-modulated data signals, the counter is respectively reset to an initial value. At the same time, a flip-flop is reset. Subsequently, the counter is counted forward by means of the clock pulses up to a predetermined counter reading which, together with the initial counter reading and the repetition frequency of the clock pulses, determines the measuring time duration. When the counter has achieved this predetermined counter reading, the flip-flop is set and it remains set until it is reset by the next edge or by a corresponding zero passage of the frequency-modulated data signals. In case the counter is simultaneously blocked with the setting of the flip-flop, then the duration of the signal setting the flip-flop directly indicates the difference of the time duration between the edges or the zero passages of the frequency-modulated data signals and the measuring time duration. This signal is filtered by employment of a low pass filter. The momentary values of the signals at the output of the low pass filter are allocated to the repetition frequencies of the corresponding frequency-modulated data signals at the input of the demodulator. A threshold value stage is connected thereafter to the low pass filter. This threshold value stage generates binary demodulated data signals whose binary values are allocated to the characteristic frequencies of the frequency-modulated data signals.
In case the frequency-modulated data signals are affected by frequency deviations, the demodulated data signals exhibit step distortions which occur in that a DC corresponding to the frequency deviation is superimposed on the signals at the input of the threshold value stage.
In order to eliminate these step distortions, it is already known from U.S. Pat. No. 3,688,205, incorporated herein by reference, to compensate the superimposed DC at the output of the low pass filter. However, this circuit requires a relatively large expense since it employs switching elements of analog circuit technology. It also depends on temperature and voltage fluctuations and, moreover, cannot be employed given intermittent operation.